Timetec Hynix 32gb ECC SODIMM compatibility?

I was wondering how likely the Timetec Hynix IC 32GB DDR4 3200MHz PC4-25600 Unbuffered ECC UDIMM 1.2V CL22 2Rx8 Dual Rank 260 Pin SODIMM Memory RAM Module Upgrade (32GB) memory @ https://smile.amazon.com/Timetec-3200MHz-PC4-25600-Unbuffered-Upgrade/dp/B09BH2BX6Q is likely to work with the Ten64? I’m looking for 32gb with ECC.

It’s about $70 USD cheaper than the best price I have found for the 9SIA6ZPCYE7376 / Kingston 32GB DDR4 2666MHz 260pin ECC Reg SoDIMM Memory Module KSM26SED8/32ME.

I’m pretty comfortable with concepts around SPD and DDR training having worked on LiteDRAM (a fully open source DDR memory controller for FPGAs) in the past but don’t necessarily know the exact details for NXP part.

Looks like a ‘G’ design SODIMM so should be ok.

I believe we have implemented support for all SODIMM designs currently in circulation (excluding some early <=2400MT/s designs). The main compatibility issue I’ve seen is where the SPDs have completely incorrect details (looking at you, Crucial).

This SODIMM module seems to be working fine in my Ten64. Some details;

INFO:    DDR PLL 2100000000
INFO:    time base 11 ms
INFO:    Parse DIMM SPD(s)
INFO:    Controller 0
INFO:    DIMM 0
INFO:    addr 0x51
WARNING: Using I2C3 for DDR SPD
WARNING: Using I2C3 for DDR SPD
WARNING: Using I2C3 for DDR SPD
WARNING: Using I2C3 for DDR SPD
INFO:    checksum 0xe9486cb
INFO:    n_ranks 2
INFO:    rank_density 0x400000000
INFO:    capacity 0x800000000
INFO:    die density 0x6
INFO:    primary_sdram_width 64
INFO:    ec_sdram_width 8
INFO:    device_width 8
INFO:    package_3ds 0
INFO:    rc 0x26 (Raw card G1)
INFO:    rdimm 0
INFO:    mirrored_dimm 1
INFO:    n_row_addr 17
INFO:    n_col_addr 10
INFO:    bank_addr_bits 0
INFO:    bank_group_bits 2
INFO:    edc_config 2
INFO:    burst_lengths_bitmask 0xc
INFO:    tckmin_x_ps 625
INFO:    tckmax_ps 1600
INFO:    caslat_x 0x17ffc00
INFO:    taa_ps 13750
INFO:    trcd_ps 13750
INFO:    trp_ps 13750
INFO:    tras_ps 32000
INFO:    trc_ps 45750   
INFO:    trfc1_ps 350000
INFO:    trfc2_ps 260000
INFO:    trfc4_ps 160000
INFO:    tfaw_ps 21000  
INFO:    trrds_ps 2500  
INFO:    trrdl_ps 4900  
INFO:    tccdl_ps 5000  
INFO:    trfc_slr_ps 0  
INFO:    twr_ps 15000   
INFO:    refresh_rate_ps 7800000
INFO:    dq_mapping 0xb 
INFO:    dq_mapping 0x2b
INFO:    dq_mapping 0xc 
INFO:    dq_mapping 0x2b
INFO:    dq_mapping 0x2b
INFO:    dq_mapping 0xb 
INFO:    dq_mapping 0x16
INFO:    dq_mapping 0x36
INFO:    dq_mapping 0xc 
INFO:    dq_mapping 0x2b
INFO:    dq_mapping 0x15
INFO:    dq_mapping 0x2c
INFO:    dq_mapping 0xb 
INFO:    dq_mapping 0x35
INFO:    dq_mapping 0x16
INFO:    dq_mapping 0x36
INFO:    dq_mapping 0x16
INFO:    dq_mapping 0x36
INFO:    dq_mapping_ors 1
INFO:    DIMM 1
INFO:    done with controller 0
INFO:    cal cs
INFO:    cs_in_use = 3  
INFO:    cs_on_dimm[0] = 3
NOTICE:  UDIMM HMAA4GS7AJR8N-XN
INFO:    Time after parsing SPD 562 ms
INFO:    Synthesize configurations
INFO:    cs 0
INFO:         odt_rd_cfg 0x0
INFO:         odt_wr_cfg 0x5
INFO:         odt_rtt_norm 0x3
INFO:         odt_rtt_wr 0x0
INFO:         auto_precharge 0
INFO:    cs 1
INFO:         odt_rd_cfg 0x0
INFO:         odt_wr_cfg 0x0
INFO:         odt_rtt_norm 0x0
INFO:         odt_rtt_wr 0x0
INFO:         auto_precharge 0
INFO:    cs 2
INFO:         odt_rd_cfg 0x0
INFO:         odt_wr_cfg 0x0
INFO:         odt_rtt_norm 0x0
INFO:         odt_rtt_wr 0x0
INFO:         auto_precharge 0
INFO:    cs 3
INFO:         odt_rd_cfg 0x0
INFO:         odt_wr_cfg 0x0
INFO:         odt_rtt_norm 0x0
INFO:         odt_rtt_wr 0x0
INFO:         auto_precharge 0
INFO:    ctlr_init_ecc 1
INFO:    x4_en 0
INFO:    ap_en 0
INFO:    ctlr_intlv 0   
INFO:    ctlr_intlv_mode 0
INFO:    ba_intlv 0x40  
INFO:    data_bus_used 0
INFO:    otf_burst_chop_en 1
INFO:    burst_length 0x6
INFO:    dbw_cap_shift 0
INFO:    Assign binding addresses
INFO:    ctlr_intlv 0   
INFO:    rank density 0x400000000
INFO:    CS 0
INFO:        base_addr 0x0
INFO:        size 0x800000000
INFO:    CS 1
INFO:        base_addr 0x0
INFO:        size 0x800000000
INFO:    base 0x0
INFO:    Total mem by assignment is 0x800000000
INFO:    Calculate controller registers
INFO:    Skip CL mask for this speed 0x4000
INFO:    Skip caslat 0x4000
INFO:    cs_in_use = 0x3
INFO:    cs0
INFO:       _config = 0x80050522
INFO:    cs[0].bnds = 0x7ff
INFO:    cs_in_use = 0x3
INFO:    cs1
INFO:       _config = 0x80000522
INFO:    cs[1].bnds = 0x7ff
INFO:    sdram_cfg[0] = 0xe5004000
INFO:    sdram_cfg[1] = 0x401151
INFO:    sdram_cfg[2] = 0x0
INFO:    timing_cfg[0] = 0xd1770018
INFO:    timing_cfg[1] = 0xf2fc8245
INFO:    timing_cfg[2] = 0x594197
INFO:    timing_cfg[3] = 0x2161100
INFO:    timing_cfg[4] = 0x220002
INFO:    timing_cfg[5] = 0x5401400
INFO:    timing_cfg[6] = 0x0
INFO:    timing_cfg[7] = 0x26600000
INFO:    timing_cfg[8] = 0x5446a00
INFO:    timing_cfg[9] = 0x0
INFO:    dq_map[0] = 0x2eb32bac
INFO:    dq_map[1] = 0x2d6d95b0
INFO:    dq_map[2] = 0x2f55b658
INFO:    dq_map[3] = 0xd8cac001
INFO:    sdram_mode[0] = 0x3010631
INFO:    sdram_mode[1] = 0x100200
INFO:    sdram_mode[9] = 0x8400000
INFO:    sdram_mode[8] = 0x500
INFO:    sdram_mode[2] = 0x10631
INFO:    sdram_mode[3] = 0x100200
INFO:    sdram_mode[10] = 0x400
INFO:    sdram_mode[11] = 0x8400000
INFO:    sdram_mode[4] = 0x10631
INFO:    sdram_mode[5] = 0x100200
INFO:    sdram_mode[12] = 0x400
INFO:    sdram_mode[13] = 0x8400000
INFO:    sdram_mode[6] = 0x10631
INFO:    sdram_mode[7] = 0x100200
INFO:    sdram_mode[14] = 0x400
INFO:    sdram_mode[15] = 0x8400000
INFO:    eor = 0x40000000
INFO:    interval = 0x1ffe07ff
INFO:    zq_cntl = 0x8a090705
INFO:    ddr_sr_cntr = 0x0
INFO:    clk_cntl = 0x2400000
INFO:    cdr[0] = 0x80080000
INFO:    cdr[1] = 0xc0  
INFO:    wrlvl_cntl[0] = 0x8675f605
INFO:    wrlvl_cntl[1] = 0x704080b
INFO:    wrlvl_cntl[2] = 0xf0c0d0a
INFO:    debug[28] = 0x7b
INFO:    Time before programming controller 830 ms
INFO:    Program controller registers
INFO:    total size 32 GB
NOTICE:  32 GB DDR4, 64-bit, CL=15, ECC on, CS0+CS1
DRAM:  31.9 GiB
DDR    31.9 GiB (DDR4, 64-bit, CL=15, ECC on)
       DDR Chip-Select Interleaving Mode: CS0+CS1
        31.4 GiB available for userspace